Programmable logic devices, such as a complex programmable logic device (CPLD), typically include a number of independent logic blocks interconnected by a global or centralized routing structure. For example, FIG. 1 illustrates a block diagram of a conventional CPLD 10 that includes a routing structure 100 and sixteen logic blocks 102, with each logic block 102 having 16 macrocells (not illustrated) and receiving 36 inputs from routing structure 100. The architecture of the logic block and of the routing structure (or interconnect) are two significant factors that determine the density, performance, and scalability of a CPLD.
Each logic block 102 in conventional CPLD 10 includes a programmable AND array (not illustrated) that a user configures to provide product term outputs of the true and complement form of the logical inputs received from routing structure 100. The product terms may be summed and the resulting sum of product terms registered in the macrocells within each logic block 102. The number of logical inputs that may factor into each product term is referred to as the “input width” for a given logic block and is fixed by the routing structure configuration. With respect to FIG. 1, the input width for logic blocks 102 is thirty-six. Another metric for a logic block is its depth, which is determined by the number of product terms that may be summed and registered within each macrocell. Just like the input width, the depth is fixed according to the configuration of a given macrocell.
Users often require relatively wide input logic blocks providing a high density of macrocells to implement complex functions such as decoders. However, as just described, conventional CPLD logic blocks are implemented with a fixed input width such that users may achieve a higher input width only by cascading product terms through the routing structure. This cascading for a portion of CPLD 10 is shown in FIG. 2. Logic block 102a provides logical outputs (either product terms or sum of product terms) having an input width of up to 36 inputs to routing structure 100 to be routed to logic block 102b. At logic block 102b, the cascaded logical outputs are “ANDed” with up to 35 additional logical inputs to provide logical outputs having a maximum input width of 71 logical variables. In turn, the logical outputs from logic block 102b may be cascaded through routing structure 100 and “ANDed” with up to 35 additional logical inputs at logic block 102c to provide logical outputs having a maximum input width of 106 logical variables. Finally, the logical outputs from logic block 102c may be cascaded through routing structure 100 and “ANDed” with up to 35 additional logical inputs at logic block 102d to provide logical outputs having a maximum input width of 141 logical variables.
Although the width cascading discussed with respect to FIG. 2 provides greater flexibility to users, this flexibility is associated with routing structure burdens and routing structure delays. Accordingly, there is a need in the art for logic blocks having enhanced width cascading ability.